Ethernet beyond 100 GbE uses more complex modulation like PAM-4 for both optical and electrical signaling. At lower speeds, links could be considered error free at the ‘bit’ level but at beyond 100 GbE we now see background bit errors. The FEC logic used in high-speed Ethernet can detect and correct many errors but it is critical to fingerprint the error profile to determine how much margin a real system may have.
This previously-recorded webinar is focused on helping people involved with developing & validating new high speed Ethernet equipment and gives them a grounding in the troubleshooting and validation in and around PAM-4 and FEC based Ethernet in a lab environment. Learn from the VIAVI experts in the physical layer and see how the impacts ripple all the way into the key Ethernet functional blocks like FEC, alignment markers and SERDES.
Join Dr. Paul Brooks, Director of Product and Technology Support, L&P for VIAVI as he explores what it takes to develop and validate new High Speed Ethernet equipment.